Computer aided design (CAD) systems for the design of electronic circuits assist in the design of electronic circuits by providing a user with a set of software tools running on a digital computer with a graphical display device. Typically, several software programs including a schematic editor, a logic compiler, a logic simulator, a logic verifier, and a layout program form a CAD system. The schematic editor program allows the user of the system to enter and/or modify a schematic diagram using the display screen, generating a net list in the process. The logic compiler takes the net list as an input, and using a component database puts all of the information necessary for layout, verification and simulation into a netlist object file or files whose format can be optimized specifically for those functions. The logic verifier checks the netlist for design errors, such as multiple outputs connected together, overloaded signal paths, etc., and generates error indications if problems exist. The logic simulator takes the netlist object file or files and simulation models, and generates a set of simulation results, acting on instructions initial conditions and input signal values provided to it either in the form of a file or user input. The layout program generates data from which a semiconductor chip or a circuit board may be laid out and produced.
Electrical engineers can use a Hardware Description Language (HDL) to specify an electrical circuit. They use special synthesis programs to produce a netlist description of that circuit. It is often useful for them to look at a graphical representation of the intermediate or final product of the synthesis program. The intermediate form of the data is often referred to as an RTL (Register Transfer Logic) description of the design. The final form is often referred to as a Technology description of the design. The present invention applies to both descriptions of the design. Engineers typically write the HDL description in terms of single nets, and groups of nets, known as buses. The synthesis process typically results in an RTL and Technology description only in terms of single nets where no buses are used. The resultant diagrams or schematics using single nets are typically complicated and difficult to follow for most users. Furthermore, a schematic using single nets makes it more difficult for a user to determine if the synthesis tool operated properly. The analysis in understanding the critical timing paths of a particular design or circuit performance based on simulation or implementation data is likewise further complicated. Thus, a need exists for a method for generating simplified netlists and schematics utilizing bus information.